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| draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra 1. general description the lpc81xm are an arm cortex-m0+ based, low-cost 32-bit mcu family operating at cpu frequencies of up to 30 mhz. the lpc81xm support up to 16 kb of flash memory and 4 kb of sram. the peripheral co mplement of the lpc81xm includes a crc engine, one i 2 c-bus interface, up to three usarts, up to two spi interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one co mparator, function-configurable i/o ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose i/o pins. 2. features and benefits ? system: ? arm cortex-m0+ processor, running at frequencies of up to 30 mhz with single-cycle multiplier and fast single-cycle i/o port. ? arm cortex-m0+ built-in nested vectored interrupt controller (nvic). ? system tick timer. ? serial wire debug (swd) and jtag boundary scan modes supported. ? micro trace buffer (mtb) supported. ? memory: ? 16 kb on-chip flash programming memory with 64 byte page write and erase. ? 4 kb sram. ? rom api support: ? boot loader. ? usart drivers. ? i2c drivers. ? power profiles. ? flash in-application programming (iap) and in-system programming (isp). ? digital peripherals: ? high-speed gpio interface connected to th e arm cortex-m0+ io bus with up to 18 general-purpose i/o (gpio) pins with co nfigurable pull-up/p ull-down resistors. ? gpio interrupt generation cap ability with boolean pattern-m atching feature on eight gpio inputs. ? switch matrix for flexible config uration of each i/o pin function. ? state configurable timer (sct) with input an d output functions (including capture and match) assigned to pins through the switch matrix. lpc81xm 32-bit arm cortex-m0+ microcontrolle r; up to 16 kb flash and 4 kb sram rev. 1.0 ? 7 november 2012 objective data sheet
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 2 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller ? multiple-channel multi-rate timer (mrt) for repetitive interrupt generation at up to four programmable, fixed rates. ? self wake-up timer (wkt) clocked from either the irc or a low-power, low-frequency internal oscillator. ? crc engine. ? windowed watchdog timer (wwdt). ? analog peripherals: ? comparator with external voltage reference with pin functions assigned or enabled through the switch matrix. ? serial interfaces: ? three usart interfaces with pin functions assigned through the switch matrix. ? two spi controllers with pin functions assigned through the switch matrix. ? one i 2 c-bus interface with pin functions assigned through the switch matrix. ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. ? crystal oscillator with an operat ing range of 1 mhz to 25 mhz. ? programmable watchdog oscillator with a frequency range of 9.4 khz to 2.3 mhz. ? 10 khz low-power oscillator for the wkt. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the system oscilla tor, the external clock input clkin, or the in ternal rc oscillator. ? clock output function with divi der that can reflec t the crystal oscillator, the main clock, the irc, or the watchdog oscillator. ? power control: ? integrated pmu (power management unit) to minimize power consumption. ? reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. ? power-on reset (por). ? brownout detect. ? unique device serial number for identification. ? single power supply. ? available as so20 package, tssop20 package, tssop16, and dip8 package. 3. applications ? 8/16-bit applications ? lighting ? consumer ? motor control ? climate control ? fire and security applications draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 3 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc810m021fn8 dip8 plastic dual in-line package; 8 leads (300 mil) sot097-2 lpc811m001fdh16 tssop16 plastic thin shrink small ou tline package; 16 leads; body width 4.4 mm sot403-1 lpc812m101fdh16 tssop16 plastic thin shrink small ou tline package; 16 leads; body width 4.4 mm sot403-1 lpc812m101fd20 so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 LPC812M101FDH20 tssop20 plastic thin shrink small ou tline package; 20 leads; body width 4.4 mm sot360-1 table 2. ordering options type number flash/kb sram/kb usart i 2 c spi comparator gpio package lpc810m021fn8 4 1 2 1 1 1 6 dip8 lpc811m001fdh16 8 2 2 1 1 1 14 tssop16 lpc812m101fdh16 16 4 3 1 2 1 14 tssop16 lpc812m101fd20 16 4 2 1 1 1 18 so20 LPC812M101FDH20 16 4 3 1 2 1 18 tssop20 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 4 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 5. block diagram fig 1. lpc81xm block diagram !"#! $ %&' !#&()#"$ $"%*+ $"%*+ $"%*+ $"%*+ $"%*+ $! , , -./0,1 -./0,1 2 , 2 3 3 3 - 3 3 - 4 3 3 3 3 3 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 5 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 6. pinning information 6.1 pinning fig 2. pin configuration dip8 package (lpc810m021fn8) ,-5 ,-,- ,- 4 ,-/ 4 ,- ,-- / 5 6 fig 3. pin configuration tssop16 package ,-/ ,-,- ,- ,-4 ,-5 ,-6 ,- 4 ,-/ 4 ,- ,-3 ,- ,-73 ,-, ,-- / 5 6 , 7 / 5 fig 4. pin configuration so20 package (lpc812m101fd20) ,-6 ,- ,-/ ,-,- ,- ,-4 ,-5 ,-6 ,- 4 ,-/ 4 ,- ,-3 ,- ,-73 ,-, ,-- ,- ,-5 / 5 6 7 , / 5 6 , 7 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 6 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller fig 5. pin configuration tssop20 package ,-6 ,- ,-/ ,-,- ,- ,-4 ,-5 ,-6 ,- 4 ,-/ 4 ,- ,-3 ,- ,-73 ,-, ,-- ,- ,-5 / 5 6 7 , / 5 6 , 7 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 7 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 6.2 pin description the pin description table ta b l e 3 shows the pin functions that are fixed to specific pins on each package. these fixed-pin functions ar e selectable between the gpio, comparator, swd, and the xtal pins. by default, the gp io function is selected except on pins pio0_2, pio0_3, and pio0_5. jtag functions are available in boundary scan mode only. movable function for the i2c, usart, spi, and sct pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin?s fixed functions. the following exceptions apply: for full i2c-bus compatibility, as sign the i2c function s to the open-drain pins pio0_11 and pio0_10. do not assign more than one output to any pin. however, more than one input can be assigned to a pin. pin pio0_4 triggers a wake-up from deep pow er-down mode. if you need to wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. the jtag functions tdo, tdi, tck, tms, and trst are selected on pins pio0_0 to pio0_4 by hardware when the part is in boundary scan mode. table 3. pin description table (fixed pins) symbol so20/ tssop20 tssop16 dip8 type reset state [1] description pio0_0/acmp_i1/ tdo 19 16 8 [5] i/o i; pu pio0_0 ? general purpose digital in put/output port 0 pin 0. in isp mode, this is the usart0 receive pin u0_rxd. in boundary scan mode: tdo (test data out). ai - acmp_i1 ? analog comparator input 1. pio0_1/acmp_i2/ clkin/tdi 12 9 5 [5] i/o i; pu pio0_1 ? general purpose digital in put/output pin. isp entry pin. a low level on this pin during reset starts the isp command handler. in boundary scan mode: tdi (test data in). ai - acmp_i2 ? analog comparator input 2. i- clkin ? external clock input. swdio/pio0_2/tms 7 6 4 [2] i/o i; pu swdio ? serial wire debug i/o. swdio is enabled by default on this pin. in boundary scan mode: tms (test mode select). i/o - pio0_2 ? general purpose digital input/output pin. swclk/pio0_3/ tck 653 [2] i/o i; pu swclk ? serial wire clock. swclk is enabled by default on this pin. in boundary scan mode: tck (test clock). i/o - pio0_3 ? general purpose digital input/output pin. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 8 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [1] pin state at reset for default function: i = input; ai = anal og input; o = output; pu = internal pull-up enabled (pins pulle d up to full v dd level ); ia = inactive, no pull-up/down enabled. [2] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis; includes high-current output driver. [3] true open-drain pin. i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. do not use this pad for high-spee d applications such as spi or usart. pio0_4/wakeup/ trst 542 [6] i/o i; pu pio0_4 ? general purpose digita l input/output pin. in isp mode, this is the usart0 transmit pin u0_txd. in boundary scan mode: trst (test reset). this pin triggers a wake-up from deep power-down mode. if you need to wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. pull this pin high externally to enter deep power-down mode. pull this pin low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. reset /pio0_5 4 3 1 [4] i/o i; pu reset ? external reset input: a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their def ault states, and processor execution to begin at address 0. i- pio0_5 ? general purpose digita l input/output pin. pio0_6/vddcmp 18 15 - [9] i/o i; pu pio0_6 ? general purpose digital input/output pin. ai - vddcmp ? alternate reference voltage for the analog comparator. pio0_7 17 14 - [2] i/o i; pu pio0_7 ? general purpose digital input/output pin. pio0_8/xtalin 14 11 - [8] i/o i; pu pio0_8 ? general purpose digital input/output pin. i- xtalin ? input to the oscillator circuit and internal clock generator circuits. input vo ltage must not exceed 1.95 v. pio0_9/xtalout 13 10 - [8] i/o i; pu pio0_9 ? general purpose digital input/output pin. o- xtalout ? output from the oscillator circuit. pio0_10 9 8 - [3] iia pio0_10 ? general purpose digital input/output pin. assign i2c functions to this pin when true open-drain pins are needed for a signal compliant with the full i2c specification. pio0_11 8 7 - [3] iia pio0_11 ? general purpose digital in put/output pin. assign i2c functions to this pin when true open-drain pins are needed for a signal compliant with the full i2c specification. pio0_12 3 2 - [2] i/o i; pu pio0_12 ? general purpose digital input/output pin. pio0_13 2 1 - [2] i/o i; pu pio0_13 ? general purpose digital input/output pin. pio0_14 20 - - [7] i/o i; pu pio0_14 ? general purpose digital input/output pin. pio0_15 11 - - [7] i/o i; pu pio0_15 ? general purpose digital input/output pin. pio0_16 10 - - [7] i/o i; pu pio0_16 ? general purpose digital input/output pin. pio0_17 1 - - [7] i/o i; pu pio0_17 ? general purpose digital input/output pin. v dd 15 12 6 - - 3.3 v supply voltage. v ss 16 13 7 - ground. table 3. pin description table (fixed pins) symbol so20/ tssop20 tssop16 dip8 type reset state [1] description draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 9 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [4] see figure 10 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [5] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog input . when configured as an analog input, the digital section of t he pin is disabled, and the pin is not 5 v tolerant. [6] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. in deep power-down mode, pulling this pin low wakes up the chip. [7] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [8] 5 v tolerant pin providing standard digital i/o functions wi th configurable modes, configur able hysteresis, and analog i/o f or the system oscillator. when configured as an analog i/o, the digital section of the pin is disabled, and the pin is not 5 v tolerant. [9] the digital part of this pin is 3 v tolerant pin due to s pecial analog functionality. pin pr ovides standard digital i/o func tions with configurable modes, confi gurable hysteresis, and an analog input. when configur ed as an analog input, the digital section of th e pin is disabled . table 4. movable functions (assi gn to pins pio0_0 to pio_17 through switch matrix) function name type description u0_txd o transmitter output for usart0. u0_rxd i receiver input for usart0. u0_rts o request to send output for usart0. u0_cts i clear to send input for usart0. u0_sclk i/o serial clock input/output for usart0 in synchronous mode. u1_txd o transmitter output for usart1. u1_rxd i receiver input for usart1. u1_rts o request to send output for usart1. u1_cts i clear to send input for usart1. u1_sclk i/o serial clock input/output for usart1 in synchronous mode. u2_txd o transmitter output for usart2. u2_rxd i receiver input for usart2. u2_rts o request to send output for usart2. u2_cts i clear to send input for usart2. u2_sclk i/o serial clock input/output for usart2 in synchronous mode. spi0_sck i/o serial clock for spi0. spi0_mosi i/o master out slave in for spi0. spi0_miso i/o master in slave out for spi0. spi0_ssel i/o slave select for spi0. spi1_sck i/o serial clock for spi1. spi1_mosi i/o master out slave in for spi1. spi1_miso i/o master in slave out for spi1. spi1_ssel i/o slave select for spi1. ctin_0 i sct input 0. ctin_1 i sct input 1. ctin_2 i sct input 2. ctin_3 i sct input 3. ctout_0 o sct output 0. ctout_1 o sct output 1. ctout_2 o sct output 2. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 10 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller ctout_3 o sct output 3. i2c0_scl i/o i 2 c-bus clock input/output (open-drain if assigned to pin pio0_10). high-current sink only if a ssigned to pio0_10 and if i 2 c fast-mode plus is selected in the i/o configuration register. i2c0_sda i/o i 2 c-bus data input/output (open-drai n if assigned to pin pio0_11). high-current sink only if assigned to pin pio0_11 and if i 2 c fast-mode plus is selected in the i/o configuration register. acmp_o o analog comparator output. clkout o clock output. gpio_int_bmat o output of the pattern match engine. table 4. movable functions (assi gn to pins pio0_0 to pio_17 through switch matrix) function name type description draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 11 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7. functional description 7.1 arm cortex-m0+ core the arm cortex-m0+ core runs at an operating frequency of up to 30 mhz using a two-stage pipeline. integrated in the core ar e the nvic and serial wire debug with four breakpoints and two watchpoints. the arm co rtex-m0+ core supports a single-cycle i/o enabled port for fast gpio access. the core includes a single-cycle multiplier and a system tick timer. 7.2 on-chip flash program memory the lpc81xm contain up to 16 kb of on-chip flash program memory. the flash memory supports a 64 byte page size with page write and erase. 7.3 on-chip sram the lpc81xm contain a total of 1 kb, 2 kb, or 4 kb on-chip static ram data memory. 7.4 on-chip rom the 8 kb on-chip rom contains the boot loader and the following application programming interfaces (api): ? in-system programming (isp) and in-application programming (iap) support for flash programming ? power profiles for configuring po wer consumption and pll settings ? usart driver api routines ? i 2 c-bus driver api routines 7.5 nested vectored inte rrupt controller (nvic) the nested vectored interrupt controller (nvic) is an integral part of the cortex-m0+. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.5.1 features ? controls system exceptions and peripheral interrupts. ? in the lpc81xm, the nvic supports 32 vectored interrupts including up to 8 external interrupt inputs selectable from all gpio pins. ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interrupt generation using the arm exceptions svcall and pendsv. ? relocatable interrupt vector table. 7.5.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 12 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller up to eight pins, regardless of the selected function, can be programmed to generate an interrupt on a level, a rising or falling edge, or both. the interrupt g enerating pins can be selected from all digital or mixed digital/anal og pins. the pin interrupt/pattern match block controls the edge or level detection mechanism. 7.6 system tick timer the arm cortex-m0+ includes a 24-bit system tick timer (systick) that is intended to generate a dedicated systick exception at a fixed time interval (typically 10 ms). 7.7 memory map the lpc81xm incorporates severa l distinct memory regions. figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the arm private peripheral bu s includes the arm core registers for controlling the nvic, the system tick timer (systick), and the reduced power modes. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 13 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.8 i/o configuration the iocon block controls the configuration of the i/o pins. each digital or mixed digital/analog pin with the pio0_n designato r (except the true open-drain pins pio0_10 and pio0_11) in ta b l e 3 can be configured as follows: ? enable or disable the weak internal pull-up and pull-down resistors. ? select a pseudo open-drain mode. the input cannot be pulled up above v dd . fig 6. lpc81xm memory map 8+)98:+)%"$ ,2 ,,, ,,, ,2 ,,, ,,, ,2 ,,, ,,, ,2 ,, ,,,, ,2 ,, ,,, ,2 ,, ,,,, ,2 ,, ,,, ,2 ,,/ ,,, ,2 ,,/ ,,, ,2 ,, ,,,, ,2 ,, ,,, ,2 ,, ,,, ,2 ,, ,,, ,2 ,,5 ,,,, ,2 ,,5 ,,, ,2 ,,5 ,,, ,2 ,, ,,,, ,2 ,, ,,, ,2 ,, ,,,, ,2 ,, ,,, ,2 ,, ,,, ,2 ,, ,,, ,2 ,,, ,,,, $+"; <% +=8 (9>+) / )+$+)*+' %&%"#? !#>8%)%(#) ,2 ,, ,,, )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' ,2 ,,/ ,,,, ,2 ,,/ ,,, , / 5 6 7 5 6 )+$+)*+' )+$+)*+' ,2,,,, ,,,, , ,@5 ,2,,, ,,,, ,2 ,,,, ,2 ,,, ,2,,, ,,,, ,25,,, ,,,, ,25,,, ,,, ,2 )+$+)*+' )+$+)*+' )+$+)*+' ,2 ,,, ,,,, ,2 ,, ,,,, 8+)98:+)%"$ ,25,,, ,,, ,2,,, ,,,, ,2,,, ,,, ,2,,, ,,, 89& 9&(+))=8($8%((+)& >%(!: ,2,,, , ,, a,b ,2,,, ,,, ab ,2,,, ,,, ab ,2 ,, ,,,, ,2 ,, ,,, ,2,,,, ,,, ,2,,,, ,,, ,2,,,, ,,, #&!:98 ;"%$: ab #&!:98 ;"%$: ab #&!:98 ;"%$: a,b c##( ,2,,,, ,,,, ,2,,,, ,,, %!(9*+ 9&(+))=8( *+!(#)$ )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' ;"%$: !#&()#""+) , $<9(!: >%()92 ,2 ,,5 ,,, 7 / , ,2 ,, ,,, ,2 ,, ,,, ,2 ,,6 ,,,, ,2,,, ,,,, ,2,, ,,,, 8)9*%(+ 8+)98:+)%" c=$ , 5 6 )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' )+$+)*+' , / draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 14 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller ? program the input glitch filter with differ ent filter constants using one of the iocon divided clock signals (ioconclkcdiv, see figure 9 ? lpc81xm clock generation ? ). you can also bypass the glitch filter. ? invert the input signal. ? hysteresis can be en abled or disabled. ? for pins pio0_10 and pio0_11, select the i2c-mode and output driver for standard digital operation, for i2c standard and fast modes, or for i2c fast mode+. ? on mixed digital/analog pins, enable t he analog input mode. enabling the analog mode disconnects the digital functionality. remark: the functionality of each i/o pin is flexib le and is determined entirely through the switch matrix. see section 7.9 for details. 7.8.1 standard i/o pad configuration figure 7 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with co nfigurable open-drain output ? digital input: weak pull-up resistor (pmos device) enabled/disabled ? digital input: weak pull-down resistor (nmos device) enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input glitch f ilter selectable on all pins ? analog input draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 15 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.9 switch matrix (swm) the switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowin g to connect many functions like the usart, spi, sct, and i2c functions to any pin that is not power or ground. these functions are called movable functions and are listed in table 4 . functions that need sp ecialized pads like the oscillato r pins xtalin and xtalout can be enabled or disabled through the switch matrix. these functions are called fixed-pin functions and cannot move to other pins. the fixed-pin functions are listed in ta b l e 3 . if a fixed-pin function is disabled, any other mov able function can be assigned to this pin. 7.10 fast general-purpo se parallel i/o (gpio) device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc81xm use accelerated gpio functions: ? gpio registers are located on the arm co rtex m0+ io bus for fastest possible single-cycle i/o timing. fig 7. standard i/o pad configuration 4 4 4 $()#&? 8=""=8 $()#&? 8=""'#<& 4 <+% 8=""=8 <+% 8=""'#<& #8+&')%9& +&%c"+ #=(8=( +&%c"+ )+8+%(+) >#'+ +&%c"+ 8=""=8 +&%c"+ 8=""'#<& +&%c"+ $+"+!( '%(% 9&*+)(+) '%(% #=(8=( '%(% 9&8=( $+"+!( ?"9(!: ;9"(+) %&%"#? 9&8=( $+"+!( %&%"#? 9&8=( 89& !#&;9?=)+' %$ '9?9(%" #=(8=( ')9*+) 89& !#&;9?=)+' %$ '9?9(%" 9&8=( 89& !#&;9?=)+' %$ %&%"#? 9&8=( draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 16 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller ? an entire port value can be written in one instruction. ? mask, set, and clear operations are supported for the entire port. all gpio port pins are fixed-pi n functions that are enabled or disabled on the pins by the switch matrix. therefore each gpio port pin is assigned to one specific pin and cannot be moved to another pin. except for pi ns swdio/pio0_2, swclk/pio0_3, and reset /pio0_5, the switch matrix enables the gpio port pin function by default. 7.10.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to inputs with internal pull-up resistors enabled after reset - except for the i 2 c-bus true open-drain pins pio0_2 and pio0_3. ? pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the iocon block for each gpio pin (see figure 7 ). ? control of the digital output slew rate allo wing to switch more ou tputs simultaneously without degrading the power/gro und distribution of the device. 7.11 pin interrupt/pattern match engine the pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the nvic. the pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. any digital pin, independently of the function selected through the switch matrix, can be configured through the syscon block as input to the pin interrupt or pattern match engine. the registers that control the pin inte rrupt or pattern match engine are located on the io+ bus for fast single-cycle access. 7.11.1 features ? pin interrupts ? up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrup t on rising or falling edges or both. ? level-sensitive interrupt pins can be high- or low-active. ? pin interrupts can wake up the lpc81xm from sleep mode, deep-sleep mode, and deep power-down mode. ? pin interrupt pattern match engine ? up to 8 pins can be selected from all digital pins to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each minters (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 17 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller ? any occurrence of a pattern match can be programmed to also generate an rxev notification to the arm cpu. the rxev signal can be connected to a pin. ? the pattern match engine d oes not facilitate wake-up. 7.12 usart0/1/2 remark: usart0 and usart1 are available on all lpc800 parts. usart2 is available on parts lpc812m101fdh16 and LPC812M101FDH20 only. all usart functions are movable functions a nd are assigned to pins through the switch matrix. 7.12.1 features ? maximum bit rates of 1.875 mbit/s in asynchronous mode and 30 mbit/s in synchronous mode for usart functions connec ted to all digital pins except pio0_10 and pio0_11. ? 7, 8, or 9 data bits and 1 or 2 stop bits ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? multiprocessor/multidrop (9-bit) mode with software address compare. (rs-485 possible with software address detection and transceiver direction control.) ? parity generation and checking: odd, even, or none. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator. ? a fractional rate divider is shared among all uarts. ? interrupts available for receiver ready, tr ansmitter ready, receiver idle, change in receiver break detect, framing error, pari ty error, overrun, underrun, delta cts detect, and receiver sa mple noise detected. ? separate data and flow control loopback modes for testing. ? baud rate clock can also be output in asynchronous mode. ? supported by on-chip rom api. 7.13 spi0/1 remark: spi0 is available on all lpc800 parts. spi1 is available on parts lpc812m101fdh16 and LPC812M101FDH20 only. all spi functions are movable functions and are assigned to pins through the switch matrix. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 18 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.13.1 features ? maximum data rates of 30 mbit/s in sl ave and master mode for spi functions connected to all digital pins except pio0_10 and pio0_11. ? data frames of 1 to 16 bits supported directly. larger frames supported by software. ? master and slave operation. ? data can be transmitted to a slave without the need to read incoming data. this can be useful while setting up an spi memory. ? control information can optionally be writ ten along with data. this allows very versatile operation, including ?any length? frames. ? one slave select input/output with selectable polarity and flexible usage. remark: texas instruments ssi and national microwire modes are not supported. 7.14 i2c-bus interface the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. the i2c-bus functions are movable functions and can be assigned through the switch matrix to any pin. however, only the true open-drain pio0_10 and pio0_11 provide the electrical characteristic s to support the full i2c-bus specification (see ref. 1 ). 7.14.1 features ? supports standard and fast mode with data rates of up to 400 kbit/s. ? independent master, slave, and monitor functions. ? supports both multi-master and multi-master with slave functions. ? multiple i 2 c slave addresses supported in hardware. ? one slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple i 2 c bus addresses. ? 10-bit addressing supported with software assist. ? supports smbus. ? supported by on-chip rom api. ? if the i2c functions are connected to th e true open-drain pins (pio0_10 and pio0_11), the i2c supports the full i2c-bus specification: ? fail-safe operation: when the power to an i 2 c-bus device is switched off, the sda and scl pins connected to the i 2 c-bus are floating and do not disturb the bus. ? supports fast-mode plus with bit rates up to 1 mbit/s. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 19 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.15 state-configurable timer (sct) the state configurable timer can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and internal capture inputs. in addition, the sct can employ up to two different programmable st ates, which can change under the control of events, to provide co mplex timing patterns. all inputs and outputs of the sct are movable functions and are assigned to pins through the switch matrix. 7.15.1 features ? two 16-bit counters or one 32-bit counter. ? counters clocked by bus clock or selected input. ? up counters or up-down counters. ? state variable allows sequencin g across multiple counter cycles. ? the following conditions define an event: a counter match condition, an input (or output) condition, a combination of a matc h and/or and input/output condition in a specified state, and the count direction. ? events control outputs, interr upts, and the sct states. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? selected events can limit, halt, start, or stop a counter. ? supports: ? 4 inputs ? 4 outputs ? 5 match/capture registers ? 6 events ? 2 states 7.16 multi-rate timer (mrt) the multi-rate timer (mrt) provides a repetiti ve interrupt timer with four channels. each channel can be programmed with an independent time interval, and each channel operates independently fr om the other channels. 7.16.1 features ? 24-bit interrupt timer ? four channels independently counting down from individually set values ? repeat and one-shot interrupt modes 7.17 windowed watc hdog timer (wwdt) the watchdog timer resets the controller if soft ware fails to periodically service it within a programmable time window. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 20 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.17.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be se lected from the inte rnal rc oscillator (irc), or the dedicated watchdog oscilla tor (wdosc). this gives a wide range of potential timing choices of watchdog oper ation under different power conditions. 7.18 self wake-up timer (wkt) the self wake-up timer is a 32-bit, loadable down-counter. writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. when the counter is used as a wake-up timer, this write can occur just prior to entering a reduced power mode. 7.18.1 features ? 32-bit loadable down-counter. counter starts automatically when a count value is loaded. time-out generates an interrupt/wake up request. ? the wkt resides in a separate, always-on power domain. ? the wkt supports two clo ck sources. one clock sour ce originates from the always-on power domain. ? the wkt can be used for waking up the part from any reduced power mode, including deep power-down mode, or for general-purpose timing. 7.19 analog comparator (acmp) the analog comparator with selectable hysteres is can compare voltage levels on external pins and internal voltages. after power-up and after switching the input chan nels of the comparator , the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. settling times are given in ta b l e 2 3 . the analog comparator output is a movable fu nction and is assigned to a pin through the switch matrix. the comparator inputs and the voltage reference are enabled or disabled on pins pio0_0 and pio0_1 through the switch matrix. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 21 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.19.1 features ? selectable 0 mv, 10 mv ( ? 5 mv), and 20 mv ( ? 10 mv), 40 mv ( ? 20 mv) input hysteresis. ? two selectable external voltages (v dd or vddcmp on pin pio0_6); fully configurable on either positive or negative input channel. ? internal voltage reference from band gap and temperature sensor selectable on either positive or negative input channel. ? 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. ? voltage ladder source voltage is selectable from an external pin or the main 3.3 v supply voltage rail. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? interrupt outp ut is connected to nvic. ? comparator level output is c onnected to output pin acmp_o. ? the comparator output can be routed intern ally to the sct input through the switch matrix. fig 8. comparator block diagram / -.01 4 4 9&(+)&%" *#"(%?+ )+;+)+&!+ +'?+ '+(+!( $d&! !#>8%)%(#) "+*+" - !#>8%)%(#) +'?+ 4 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 22 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.20 clocking and power control 7.20.1 crystal and internal oscillators the lpc81xm include four independent oscillators: 1. the crystal oscillator (syso sc) operating at frequencie s between 1 mhz and 25 mhz. 2. the internal rc oscillator (irc) with a fi xed frequency of 12 mhz, trimmed to 1% accuracy. 3. the internal low-power, low-frequency oscillator with a nominal frequency of 10 khz with 40% accuracy for use with the self wake-up timer. 4. the dedicated watchdog oscillator (w dosc) with a programmable nominal frequency between 9.4 khz and 2.3 mhz with 40% accuracy. fig 9. lpc81xm clock generation <%(!:'#? #$!9""%(#) #$!9""%(#) #$!9""%(#) <%(!:'#? #$!9""%(#) a>%9& !"#! $+"+!(b $d$(+> !"#! $+"+!( 4 4 !"#! , a!#)+ $d$(+>e %"<%d$#&b 4 4 , #$!9""%(#) "#<8#<+) #$!9""%(#) <%(!:'#? #$!9""%(#) #$!9""%(#) $d$(+> #$!9""%(#) 4 4 89& a !"#! $+"+!(b >%9& !"#! $d$(+> !"#! .071 a$d$(+> !"#! +&%c"+b >+>#)9+$ %&' 8+)98:+)%"$ 8+)98:+)%" !"#! $ 7 4 4 ?"9(!: ;9"(+) 6 3 3 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 23 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller each oscillator, except th e low-frequency oscillator, c an be used for more than one purpose as required in a particular application. following reset, the lpc81xm will op erate from the irc until sw itched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 9 for an overview of the lpc81xm clock generation. 7.20.1.1 internal rc oscillator (irc) the irc may be used as the clock source for the wwdt, and/or as the clock that drives the pll and subsequently the cpu. the nomi nal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. the irc can be used as a clock source fo r the cpu with or without using the pll. the irc frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. upon power-up or any chip reset, the lpc81xm use the irc as the clock source. software may later switch to one of the other available clock sources. 7.20.1.2 crystal oscillator (sysosc) the crystal oscillator can be used as the clo ck source for the cpu, with or without using the pll. the sysosc operates at fre quencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. 7.20.1.3 internal low-power oscillator and watchdog oscillator (wdosc) the nominal frequency of the wdosc is prog rammable between 9.4 khz and 2.3 mhz. the frequency spread over silicon process variations is ? 40%. the wdosc is a dedicated oscillator for the windowed wwdt. the internal low-power 10 khz ( ? 40% accuracy) oscillator serves a the clock input to the wkt. this oscillator can be configur ed to run in a ll low power modes. 7.20.2 clock input a 3.3 v external clock source (25 mhz typical) can be supplied on the selected clkin pin or a 1.8 v external clock source can be supplied on the xtalin pin (see section 13.1 ). 7.20.3 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insu red that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is nominally 100 ? s. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 24 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.20.4 clock output the lpc81xm features a clock output functi on that routes the irc, the sysosc, the watchdog oscillator, or the main clock to t he clkout function. the clkout function can be connected to any digital pin through the switch matrix. 7.20.5 wake-up process the lpc81xm begin operation at power-up by using the irc as the clock source. this allows chip operation to resume quickly. if th e sysosc, the external clock source, or the pll is needed by the application, software mu st enable these features and wait for them to stabilize before they ar e used as a clock source. 7.20.6 power control the lpc81xm supports the arm cortex-m0 sleep mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this a llows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their own clock divider which provides even better power control. 7.20.6.1 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile api. the api is accessible through the on-chip rom. the power configuration routine configures the lpc81xm for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routin es to select the optimal pll settings for a given system clock and pll input clock. 7.20.6.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 25 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.20.6.3 deep-sleep mode in deep-sleep mode, the lpc81xm is in sleep-mode and all peri pheral clocks and all clock sources are off except fo r the irc and watchdog oscillato r or low-power oscillator if selected. the irc output is disabled. in additi on all analog blocks are shut down and the flash is in stand-by mode. in deep-sleep mode, the application can keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc81xm can wake up from deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the usart (if the usart is configured in synchronous slave mode), the spi, or the i2c blocks (in slave mode). any interrupt used for waking up from deep-sleep mode must be enabled in one of the syscon wake-up enable r egisters and the nvic. deep-sleep mode saves power and allows for short wake-up times. 7.20.6.4 power-down mode in power-down mode, the lp c81xm is in sleep-mode and all peripheral clocks and all clock sources are off except for watchdog osc illator or low-power osc illator if selected. in addition all analog blocks and the flash are shut down. in power-down mode, the application can keep the watc hdog oscillator and the bod circ uit running for self-timed wake-up and bod protection. the lpc81xm can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the usart (if the usart is configured in synchronous slave mode), the spi, or the i2c blocks (in slave mode). any interrupt used for waking up from power-down mode must be enabled in one of the syscon wake-up enable r egisters and the nvic. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 7.20.6.5 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the wakeup pin and the self wake-up timer if enabled. the lpc81xm can wake up from deep power-down mode via the wakeup pin, or without an external signal by using the time-out of the self wake-up timer (see section 7.18 ). the lpc81xm can be prevented from entering deep power-down mode by setting a lock bit in the pmu block. locking out deep powe r-down mode enables the application to keep the watchdog timer or the bod running at all times. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. pull the reset pin high to prevent it from floating while in deep power-down mode. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 26 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.21 system control 7.21.1 reset reset has four sources on the lpc81xm: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc an d initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. in deep power-down mode, an external pull-up resistor is required on the reset pin. 7.21.2 brownout detection the lpc81xm includes up to four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic to cause a cpu interrupt. alternatively, so ftware can monitor the signal by reading a dedicated status register. four threshold levels can be selected to cause a forced reset of the chip. 7.21.3 code security (code read protection - crp) crp provides different levels of security in th e system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. programming a specific pattern in to a dedicated flash location invokes crp. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details, see the lpc800 user manual . there are three levels of code read protection: fig 10. reset pad configuration 4 )+$+( 4 4 4 8= , &$ draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 27 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin as well. if necessary, the application must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable flash update via the usart. in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details, see the lpc800 user manual . 7.21.4 apb interface the apb peripherals are located on one apb bus. 7.21.5 ahblite the ahblite connects the cpu bus of the ar m cortex-m0+ to the flash memory, the main static ram, the crc, and the rom. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 28 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 7.22 emulation and debugging debug functions are integrated into the arm cortex-m0+. serial wire debug functions are supported in addition to a standard jtag boundary scan. the arm cortex-m0+ is configured to support up to four breakpoints and two watch points. the micro trace buffer is implemented on the lpc81xm. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc81xm is in reset. the jtag boundary scan pins are selected by hardware when the part is in boundary scan mode on pins pio0_0 to pio0_3 (see table 3 ). to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 29 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. c) the limiting values are stress ratings only and operating the pa rt at these values is not recommended and proper operation is not guaranteed. the conditions for functi onal operation are specified in table 9 . [2] maximum/minimum voltage above the maximum operating voltage (see table 9 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] including voltage on outputs in tri-state mode. does not apply to pin pio0_6. [4] v dd present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd is powered down. [5] v dd present or not present. [6] if the comparator is configured with the common mode input v ic = v dd , the other comparator input can be up to 0.2 v above or below v dd without affecting the hysteresis range of the comparator function. [7] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) [2] ? 0.5 +4.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [3] ? 0.5 +5.5 v 5 v open-drain pins pio0_10 and pio0_11 [4] ? 0.5 +5.5 v 3 v tolerant i/o pin pio0_6 [5] ? 0.5 +3.6 v v ia analog input voltage [6] [7] ? 0.5 v 4.6 v v i(xtal) crystal input voltage [2] ? 0.5 +2.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c - 100 ma t stg storage temperature non-operating [8] ? 65 +150 ? c t j(max) maximum junction temperature - 150 ? c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 30 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [8] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [9] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? + = table 6. thermal characteristics symbol parameter conditions min typ max unit t j(max) maximum junction temperature --125 ? c table 7. thermal resistance (tssop packages) symbol parameter conditions thermal resistance in ? c/w 15 % tssop16 tssop20 r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 31 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 10. static characteristics table 9. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 1.8 3.3 3.6 v i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz; default mode; v dd = 3.3 v [2] [3] [4] [6] [7] -1.4 -ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [2] [3] [4] [6] [7] - draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 32 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller v o output voltage output active 0 - draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 33 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; system oscillator disabled; system pll disabled. [5] system oscillator enabled; i rc disabled; system pll disabled. [6] bod disabled. [7] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to usart, clkout, and iocon disabled in system configuration block. [8] irc disabled; system oscill ator enabled; system pll enabled. v ol low-level output voltage 2.5 v ?? v dd ?? 3.6 v; i ol = 4 ma - - draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 34 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [9] all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 18ff. [10] wakeup pin pulled high externally. [11] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [12] including voltage on outputs in 3-state mode. [13] v dd supply voltage must be present. [14] 3-state outputs go into 3-state mode in deep power-down mode. [15] allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] to v ss . fig 11. pin input/output current measurement %%%,, , f 89& ,-& 8= f 89& ,-& 8' 4 draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 35 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 10.1 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions): ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 0 to all gpio data register to drive the outputs low. conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 36 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 37 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 15. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 16. power-down mode: typical supply current i dd versus temperature for different supply voltages v dd x (x) x x x xx 001aac984 x x x x x x (x) x draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 38 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 10.2 coremark data (1) wkt running. (1) wkt not running. fig 17. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd x (x) x x x xx 001aac984 x x x x x x (x) x draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 39 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 10.3 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator an d pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 30 mhz. table 10. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 30 mhz irc draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 40 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 10.4 electrical pi n characteristics conditions: v dd = 3.3 v and v dd = 1.8 v; on pin draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 41 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller conditions: v dd = 3.3 v and v dd = 1.8 v; standard port pins and draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 42 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller conditions: v dd = 3.3 v and v dd = 1.8 v; standard port pins. fig 23. typical pull-up current i pu versus input voltage v i conditions: v dd = 3.3 v and v dd = 1.8 v; standard port pins. fig 24. typical pull-down current i pd versus input voltage v i x (x) x x x xx 001aac984 x x x x x x (x) x draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 43 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 11. dynamic characteristics 11.1 power-up ramp conditions draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 44 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 11.4 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. fig 25. external clock timing (with an amplitude of at least v i(rms) = 200 mv) ( ( 3 ( 3 !da!" b ( ( ( 3 ( 3 !da!" b ( ( ( 3 ( 3 !da!" b ( ( ( 3 ( 3 !da!" b ( table 13. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 45 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ? 40 ? c to +85 ? c) is ? 40 %. [3] see the lpc800 user manual . [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ? 40 ? c to +85 ? c) is ? 40 %. [3] see the lpc800 user manual . 11.5 i/o pins [1] applies to standard port pins and reset pin. table 14. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz table 15. dynamic characterist ics: low-power oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency [2] [3] -9.4 - khz table 16. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 46 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 11.6 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. table 17. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus; on pins pio0_10 and pio0_11 01mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus; on pins pio0_10 and pio0_11 - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0- ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus; on pins pio0_10 and pio0_11 50 - ns draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 47 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. 11.7 spi interfaces the maximum data bit rate is 30 mbit/s in slave and master modes. remark: spi functions can be assigned to all digita l pins. the characteristics are valid for all digital pins except the open-drain pins pio0_10 and pio0_11. fig 27. i 2 c-bus pins clock timing ( ; 6, g /, g ( ; 6, g /, g 6, g /, g 6, g /, g ( e ; 6, g /, g 6, g /, g ( 4e ( ( ( e table 18. dynamic characteristics of spi pins t amb = ? 40 ? c to 85 ? c; c l = draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 48 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [1] t cy(clk) = a h ,b !da!" b ( !" ab ( !" ab ( ( ( *aib 4 4 ( :aib a h b 4 4 ( ( 4 4 ( :aib 4 4 ( *aib h h , draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 49 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 11.8 usart interface the maximum usart bit rate is 1.875 mbit/s in asynchronous mode and 30 mbit/s in synchronous mode slave and master mode. remark: usart functions can be assigned to all di gital pins. the characteristics are valid for all digital pins except the ope n-drain pins pio0_10 and pio0_11. pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 29. spi slave timing in spi mode a h ,b !da!" b ( !" ab ( !" ab ( ( ( *aib 4 4 ( :aib a h b 4 4 ( ( ( *aib 4 4 ( :aib 4 4 h h , table 19. dynamic characteri stics: usart interface in synchronous master mode t amb = ? 40 ? c to 85 ? c; 1.8 v ? v dd ? 3.6 v; c l = draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 50 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 12. analog characteristics 12.1 bod [1] interrupt levels are selected by writing the level value to the bod control register bodctrl. 12.2 por table 20. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 51 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller 12.3 comparator [1] c l = 10 pf; results from measurements on silicon samples ov er process corners and over the full temperature range t amb = -40 ? c to +85 ? c. [2] input hysteresis is relative to the referenc e input channel and is software programmable. table 22. comparator characteristics v dd(3v3) = 3.0 v and t amb = 25 ? c unless noted otherwise. symbol parameter conditions min typ max unit static characteristics i dd supply current - draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra lpc81xm all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. objective data sheet rev. 1.0 ? 7 november 2012 52 of 67 nxp semiconductors lpc81xm 32-bit arm cortex-m0+ microcontroller [1] maximum values are derived from worst case simulation (v dd = 2.6 v; t amb = 85 ? c; slow process models). [2] settling time applies to switching between comparator channels |